Good News | Three Ph.D Candidates Successfully Defend Their Dissertations at Westlake University

On June 6, the CenBRAIN Neurotech Center of Excellence, School of Engineering, Westlake University hosted a warm graduation celebration to congratulate three newly minted Ph.D Graduates: Dr. Chaoming Fang, Dr. Hui Wu and Dr. Wenjun Zou.

Under the dedicated supervision of Chair Professor Mohamad Sawan, the three scholars have devoted themselves to research and achieved remarkable breakthroughs in three cutting-edge areas, including spiking neural network processors, high-density neural recording systems, and wireless data transmission for implantable brain-computer interfaces.

When they first joined the lab, they embarked on their research journey with curiosity and exploration. After years of dedicated work and steady growth, they completed their PhD defenses with solid research outcomes. All the efforts and hardships throughout their doctoral studies have become precious lifelong memories.

To recognize their hard work and achievements, Professor Mohamad Sawan presented each of them with a commemorative figurine. The three graduates also shared their thoughts on the PhD experience and expressed sincere gratitude to Professor Sawan.

Graduates’ Thoughts

Hui Wu: CenBRAIN Neurotech is hands down one of the best places to do research. I want to thank Professor Sawan, Dr. Jie Yang and all the center members for your constant support. It has given me the freedom to follow my research passions.

Chaoming Fang: Doing my PhD here at CenBRAIN Neurotech has been an amazing experience. I’m truly grateful for Professor Sawan’s guidance, the top-tier lab resources, and all the help and teamwork from our members.

Wenjun Zou: I’d like to thank every member in the lab who has helped me along the way. My biggest thanks go to Professor Sawan. His patient advice and constant encouragement have shown me exactly how to grow into a great researcher.

Graduate Profiles

Dr. Chaoming Fang

Chaoming Fang defended his doctoral dissertation at Yungu Campus on May 20, 2026.

The defense committee was chaired by Chair Professor Yaochu Jin (Westlake University). The committee members include Professor De Ma (Zhejiang University), Professor Zhuo Zou (Fudan University), Professor Hao Yu (Southern University of Science and Technology) and Associate Professor Bowen Zhu (Westlake University). Dr. Yun-Hsuan Chen, Research Assistant Professor at Westlake University, served as the defense secretary.

Chaoming focuses on application scenarios of edge computing and devotes himself to the research on the design of low-power AI chips and neuromorphic computing chips. As the first author, he has published eight high-quality papers in top-tier international journals and conferences, including IEEE Journal of Solid-State Circuits and IEEE Transactions on Biomedical Circuits and Systems, as well as the IEEE Custom Integrated Circuits Conference(CICC) and IEEE Asian Solid-State Circuits Conference(A-SSCC).

During his doctoral studies, he received numerous honors: First Prize in the National Postgraduate IC Innovation Competition, the Suwu Scholarship, as well as the titles of Outstanding Student Leader, Merit Student and Outstanding Graduate awarded by Zhejiang University.

Dissertation Title: Energy-Efficient Spiking Neural Network Processors Based on Reconfigurable Architecture and Sparse Computing

Abstract:

Spiking neural networks (SNNs) are a promising approach for low-power artificial intelligence, but practical SNN processors still face challenges in generality, latency, and real-world deployment. Chaoming Fang’s Ph.D. dissertation focuses on energy-efficient SNN processor design, proposing reconfigurable architecture and sparse computing as two key techniques, and implements three different chips for distinct application targets. The first chip targets ultra-low-power online learning and uses a reconfigurable architecture to support multiple SNN topologies and STDP learning under a microwatt-level power budget. The second chip targets low-latency inference for large-scale SNNs, introducing a 3D computation array and sparsity-aware acceleration for efficient spiking attention and convolution operations. The third chip targets embodied intelligence and implements a 28nm spiking Vision Transformer accelerator, improving continuous visual perception through frame-differential dataflow and a reconfigurable sparse computing core. Together, these three chips form a systematic exploration from online-learning SNN processors to large-scale SNN inference accelerators and embodied-intelligence processors, providing practical hardware solutions for low-power, high-generality, and low-latency AI systems.

/List of Publications/

Dr. Hui Wu

Hui Wu completed his dissertation defense at Yungu Campus on May 21, 2026.

The defense committee was chaired by Chair Professor Wei Xie (Westlake University). The committee members include Professor Yajie Qin (Fudan University), Professor Tao Wang, Research Professor Shuang Song (Zhejiang University) and Assistant Professor Qicheng Zhang (Westlake University). Dr. Yun-Hsuan Chen, Research Assistant Professor at Westlake University, as the defense secretary.

Hui’s research focuses on front-end chip architecture for neural signal acquisition. Using analog and mixed-signal integrated circuit techniques, his work aims to realize high-fidelity recording of neuronal electrical signals. As first author and co-first author, he has published nine high-impact papers, whose findings have been presented at flagship IC conferences including the IEEE International Solid-State Circuits Conference (ISSCC) and IEEE Custom Integrated Circuits Conference (CICC). One of his papers won the Best Paper Award at the 2025 IEEE International Symposium on Circuits and Systems (ISCAS).

He has been granted one invention patent entitled An Adjustable Low-Pass Filter Circuit Based on Self-Biased Pseudoresistor, with two additional patents currently under review. Throughout his PhD program, he was repeatedly recognized as an Outstanding Graduate of Westlake University and was awarded the Suwu Scholarship for the 2023–2024 academic year.

Dissertation Title: High-Channel-Count and High-Density Neural Recording Systems: From Configurable Front-Ends to Neuromorphic Sparsity-Aware SoCs

Abstract:

The growing demand for high-channel-count, high-density neural recording systems in brain-machine interfaces exposes fundamental engineering bottlenecks in power, area, and data bandwidth. This thesis addresses these challenges through a progression of solutions, achieving a leap from single-channel optimization to a 1024-channel system integration.  

First, an energy-efficient, configurable analog front-end (CAFE) is presented. Fabricated in 40 nm CMOS, it achieves a noise efficiency factor of 4.1, an active area of 0.048 mm², and a power consumption of 2.47 µW, adapting flexibly to multimodal biosignals.

Second, a self-adaptive pseudo-resistor (A-PR) is proposed to address stimulation artifacts in closed-loop interfaces. It reduces the artifact recovery time from over 4 s to under 3 ms, providing critical robustness without sacrificing signal fidelity.

Third, to overcome area and telemetry bottlenecks, a 32-channel neuromorphic multiplexing interface, NeuroSEED, is developed. Utilizing an event-driven architecture, it achieves >500× data compression and consumes only 1.38 µW/channel. Finally, a 1024-channel sparsity-aware neural interface is realized using a predictive focused sampling strategy and a compute-in-memory (CIM) core. The CIM core intelligently allocates high-resolution sampling to active neural regions, eliminating the von Neumann bottleneck and reducing digital energy by 87%. The system achieves a remarkable 0.0011 mm²/channel area density.  

In summary, this thesis establishes a scalable framework that significantly improves noise efficiency, recovery speed, and data compression, providing essential circuit-to-architecture foundations for next-generation implantable brain-machine interfaces.

/List of Publications/

Dr. Wenjun Zou

Wenjun Zou held his dissertation defense at Yungu Campus on June 2, 2026.

The defense committee was chaired by Chair Professor Weicheng Cui (Westlake University). The committee members include Professor Hui Hong (Hangzhou Dianzi University), Research Professor Zhenghua An (Fudan University), Research Professor Jian Xu (Zhejiang University) and Assistant Professor Wei Wang (Westlake University). Dr. Hongyong Zhang, Postdoctoral Fellow at Westlake University, as the defense secretary.

His research focuses on low-power analog integrated circuit design and wireless data transmission for brain-computer interfaces. He has participated in multiple research projects and published 5 first-author papers. He has obtained one granted patent titled A Pulsed Ultra-Wideband Transmitter, accumulating rich technical expertise in wireless transmission for implantable BCIs. Additionally, he is a recipient of the Freshman Special Scholarship of Westlake University and the National Scholarship of Fudan University.

Dissertation Title: Ultra-Low-Power Wireless Data Transmission for High-Channel-Count Implantable Brain-Computer Interfaces

Abstract:

This research addresses a core challenge for high-channel-count implantable BCIs: the conflict between massive neural data transmission demands and the stringent ultra-low-power requirements for implantable devices. Based on Impulse Radio Ultra-Wideband (IR-UWB) technology, three integrated circuit solutions are proposed in this work.

The team develops an ultra-compact IR-UWB transmitter chip using 40nm CMOS process. The chip features a core area of merely 0.001 mm² and maintains a steady energy efficiency of 2.45 pJ/b across the data rate range of 10–200 Mbps. A duty-cycled phase-locked loop with voltage retention modules is innovatively designed to enable periodic self-calibration, which reduces the power consumption during idle mode to nearly zero. Combined with compact fractal antennas, the design eliminates the need for traditional on-chip matching networks.

A 1024-channel dual-mode wireless neural streaming interface system is finally implemented with a four-input single-output ultra-wideband transmitter architecture. In-vivo measurements show that the system consumes only 157 μW at a data rate of 27.5 Mbps. This research delivers a high-throughput and ultra-low-power wireless transmission solution for next-generation large-scale implantable BCIs.

Closing Remarks

The successful graduation of the three PhDs fully demonstrates the outstanding talent cultivation capacity and strong research innovation strength of the CenBRAIN Neurotech Center of Excellence. We wish them every success in their future academic and professional endeavors and look forward to their continued achievements on the research journey ahead.