Prof. Mohamad Sawan’s Group from Westlake University Contributed Three Research Achievements at IEEE NEWCAS 2026

The 24th IEEE International New Circuits and Systems Conference (NEWCAS 2026) has recently been concluded in Canada.

Dr. Mohamad Sawan, Chair Professor at Westlake University, served as the Honorary Chair, Sessions’ chair and his cofounder and one of the Steering Committee Members of NEWCAS 2026. Three innovative research achievements from CenBRAIN Neurotech Center of Excellence, led by Professor Sawan were successfully presented at the conference, contributed as first author by Dr. Razieh Eskandari (Research Assistant Professor), Dr. Wenjun Zou (2026 PhD graduate), and Xing Liu (PhD candidate).

As a regional flagship event of the IEEE Circuits and Systems Society, NEWCAS covers cutting-edge research topics spanning adaptive systems, analog and digital signal processing, low-power design, and circuits and systems, establishing itself as a key international platform for academic exchanges in the field of circuits and systems.

Three innovative contributions at IEEE NEWCAS 2026 focus on hybrid modulation technologies for ultra-wideband transmitters, low-power phase-locked loop architectures, and high-sensitivity RF energy harvesting front ends. These works jointly address the core hardware challenges of wireless neural interfaces concerning power efficiency, timing synchronization, and self-powered operation.

Detailed introductions are provided below:

Paper #1：

Eskandari R., Sawan M., “A 850 Mb/s IR-UWB Transmitter with ISI-Resilient OS-D4PPM/QPSK Hybrid Modulation”. 2026 24th IEEE International NEWCAS Conference, Canada, Jun. 2026

Abstract：

In this paper we present an impulse-radio ultrawideband (IR-UWB) transmitter with embedded synchronization and hybrid modulation. An overlapped-slot differential 4-PPM (OS-D4PPM) scheme is proposed, where information is encoded in the relative timing between a synchronization (Sync) pulse and a data pulse. This structure decouples data rate from pulse repetition frequency (PRF), enabling higher throughput without degrading link margin or bandwidth. Each symbol comprises two pulses, and controlled overlap among allowable pulse positions improves spectral efficiency while preserving strong immunity to inter-symbol interference (ISI). The explicit Sync pulse relaxes timing recovery requirements and improves robustness to jitter and slot-to-slot timing variations. To further increase modulation order without additional pulses, QPSK is applied to the data pulse. Designed and simulated in 40-nm CMOS, the transmitter achieves 850 Mb/s at a 140-MHz PRF with an energy efficiency of 3.5 pJ/b, making it well suited for energy-constrained IR-UWB applications such as high-density neural recording systems.

Fig.1. Block diagram of the proposed transmitter.

Fig.2. Simulation results of the transmitted signal at the TX antenna.

Paper #2：

Zou W., Wu H., Liu X., Chen J., Ye Y., Yang J., Sawan M., “A Duty-Cycled PLL Architecture for a Low-Power IR-UWB Transmitter in Neural Implants”. 2026 24th IEEE International NEWCAS Conference, Canada, Jun. 2026

Abstract：

We present in this paper a low-power phase-locked loop (PLL) architecture with tunable duty-cycle operation for data transmission from implantable neural recording devices. By integrating a switch-controlled voltage holding (SCVH) module, the architecture enables periodic calibration, while ensuring the voltage drop during silent phases is negligible. Implemented in TSMC 40 nm CMOS process technology, the core area is 0.0035 mm², and the post-layout simulation reveals that the proposed PLL achieves a locking frequency of 4.25 GHz in 0.5 μs and a faster relocking in subsequent calibration cycles. The average power consumption is 90 μW, reduced by 89% compared to the design without the proposed SCVH module, and the peak-to-peak jitter is 2.14 ps.

Fig.1: (a) Block diagram of a neural implant including an impulse-radio ultra-wideband (IR-UWB) wireless transmitter, and proposed hybrid PLL+VCRO_TX scheme. (b) Conventional PLL scheme for upconversion.

Paper #3：

Liu X., Wu H., Chen J., Zou W., Ye Y., Yang J., Sawan M., A High-Sensitivity Surge-Mode RF Energy Harvester for Self-Powered Devices. 24th IEEE International NEWCAS Conference, Canada, Jun. 2026.

Abstract：

We present in this paper a high-sensitivity surge-mode radio-frequency energy harvesting front-end for self-powered devices. The proposed architecture integrates an eight-stage cross-coupled differential-drive rectifier, a nanowatt-level voltage monitor, and an ultra-low-power power management unit featuring a CMOS voltage reference and adaptive flipped-voltage-follower LDO. By enabling intermittent surge-mode operation, the system effectively transforms the rectifier's load-dependent behavior into an ultra-light-load condition, achieving efficient energy accumulation under weak RF inputs. Implemented in a 40-nm CMOS process, the proposed front-end achieves a sensitivity of -22 dBm and a peak power conversion efficiency of 42.25% at 915 MHz, providing a stable and adaptive power supply for long-term maintenance-free IoT and biomedical applications.

Fig. 1. Principle of surge-mode RF energy harvesting front-end for non-stop self-powered systems.

Fig. 2. System blocks of proposed surge-mode RF energy harvesting front-end and single-stage CCDD rectifier applied in system.