Latest Research Contribution from Professor Mohamad Sawan's Center: A Neuromorphic Scalable Event-Driven SoC for Spike Detection and Wireless Telemetry

In recent years, brain–computer interface (BCI) applications have grown rapidly. They now cover areas from neurological disorder monitoring and motor control to high-fidelity speech and sensory decoding. As a result, the number of channels in implantable BCIs has increased significantly. Moore's Law has greatly improved digital circuit performance. However, analog circuits have not benefited as much from CMOS scaling. This is due to fundamental physical limits such as thermal noise, mismatch, and parasitic effects.

More importantly, when implantable BCIs channel counts reach thousands, continuous neural recording and massive wireless data transmission cause power consumption to rise sharply. This creates serious thermal safety concerns for implantable chips. Therefore, new circuit architectures are needed. They must achieve scalable and high-fidelity neural recording under strict power and area limits. They must also greatly reduce wireless data transmission without sacrificing task performance.

To tackle these challenges, CenBRAIN Neurotech Center of Excellence, led by Chair Professor Mohamad Sawan, has developed the NeuroSEED. It is a 32-channel neuromorphic scalable event-driven SoC.

Figure 1. System concept of the proposed neuromorphic neural interface.

This work has been published on the《IEEE Journal on Emerging and Selected Topics in Circuits and Systems》. The co-first authors are our Westlake University’s Ph.D. graduates, Dr. Hui Wu and Dr. Jinbo Chen. They completed their PhD studies in 2025 and 2026, respectively. The corresponding authors are Research Professor Dr. Jie Yang and Chair Professor Mohamad Sawan.

Research Highlight

1. Ultra-Compact Direct-Multiplexing Front-End Design:

We propose an area-efficient time-division multiplexed analog front-end occupying only 0.0032 mm² per channel, equipped with a dedicated digital-servo electrode DC offset cancellation feedback loop. This effectively mitigates inter-channel offset variations while significantly reducing chip area.

2. Bio-Inspired Adaptive Event-Driven Sampling:

We innovatively design an analog-to-spike converter (ASC) with an adaptive event-driven sampling mechanism. The system generates spike events only when neural signals change significantly, thereby minimizing power consumption from redundant data.

3. Clockless High-Efficiency Spike Detection and Data Compression:

We introduce a clockless spike detector that employs relative "valley-to-peak" voltage swings for robust feature identification. This mechanism not only offers excellent noise immunity but also achieves a remarkable data compression ratio of over 500×.

4. Event-Triggered Ultra-Low-Power Wireless Telemetry:

We integrate an event-triggered impulse-radio ultra-wideband (IR-UWB) transmitter, which is selectively awakened by compressed spike data. This "on-demand transmission" strategy ensures communication occurs only during valid neural events, achieving exceptional energy utilization efficiency.

Abstract

Implantable multi-channel neural interfaces are essential for high-resolution, long-term brain–computer interface applications. However, conventional designs face severe constraints in power, data bandwidth, and silicon area. Inspired by biological neuron signaling, we present NeuroSEED, a 32-channel neuromorphic scalable neural interface SoC. This system introduces four key innovations to address scalability and efficiency bottlenecks: (1) an area-efficient time-division multiplexed analog front-end (0.0032 mm²/channel) with a dedicated digital-servo electrode DC offset cancellation loop; (2) an analog-to-spike converter (ASC) that uses adaptive event-driven sampling; (3) a clockless spike detector that uses valley-to-peak detection for robust spike identification; and (4) an event-triggered impulse-radio ultra-wideband (IR-UWB) transmitter for energy-efficient wireless spike telemetry.

Figure 2. Overall block diagram of the proposed system, implementing a 32-channel direct-multiplexing front-end combined with event-driven processing.

Fabricated in 40-nm CMOS, NeuroSEED consumes only 1.38 μW per recording channel and 4.6 μW for the transmitter. It achieves more than 500× data reduction compared to Nyquist-rate sampling. Experiments with in-vivo neural datasets confirm its low noise, compact area, and robust system-level performance. These results position NeuroSEED as a highly efficient SoC for high-density neural recording.

Figure 3. Chip micrograph and performance summary.

H. Wu*, J. Chen*, R. Eskandari, Y. Han, X. Liu, W. Zou, F. Tian, Q. Hou, S. Lin, J. Yang, and M. Sawan, "NeuroSEED: A Neuromorphic Scalable Event-Driven SoC with Direct Multiplexing for Spike Detection and Wireless Telemetry," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, online, 2026.

https://doi.org/10.1109/JETCAS.2026.3705440